HAWC/SHARCII JFET Qualification Procedure -- Warm Board Assembly ================================================================ D. Dowell Caltech FAX 626-796-8806 13 June 2001 Version 5 Distribution ------------ A. Bartels, S. Babu, M. Freund, M. Jhabvala, H. Moseley, G. Voellmer (GSFC) A. Harper, D. Sandford (U. Chicago) J. Groseth (Caltech) General Plan ------------ 1) Ceramic substrates were provided by Goddard (S. Babu, M. Jhabvala) in April 2000. 2) InterFET NJ132L dies will be glued to the substrate with Epotek H70 epoxy, 128 devices per substrate. Additionally, 2 diode thermometers (Lake Shore XDT-600-NL-B) and 6 resistor heaters (MSI MSTF 2SN-20000F-G) will be epoxied to each substrate with Epotek E4110. 3) Permanent wire bonds will be made between the device bond pads and substrate bond pads. 4) The warm board will be installed in a test fixture for electrical tests at 120 K. Temporary wire bonds will be made between the test fixture and the outer bond pads on the JFET warm board. 5) Bad devices will be replaced and re-tested in order to meet the yield requirements. 6) Seven (7) boards will be delivered to Goddard for integration with the bridge chips and mechanical suspension in the JFET drawers. 7) Test results and other documentation will be made available to Goddard at the same time. Epoxy Qualification ------------------- The epoxy will be mixed and cured according to manufacturers recommendations. For each batch, we will glue one or more JFETs to a test substrate for epoxy qualification. The hardness and adhesion will be examined before and after a liquid nitrogen dip. These JFETs will be used later for wire bond qualification. The mixing and curing of the epoxy, as well as its observed properties, will be documented. Wire Bond Qualification ----------------------- The JFETs will be bonded with 0.001" diameter gold wire using a West Bond 7400B. Before and after each session of bonding devices on the substrates, the performance of the wire bonder will be evaluated. The evaluation procedure is: 1) Perform 6 wire bonds from substrate to JFET bond pads on a SEPARATE, PARTIALLY-POPULATED board. 2) Perform 6 wire bonds from substrate to substrate on the fully-populated warm board. 3) Pull test wire bonds from steps (1) and (2) to breaking (destructive testing). All wire bonds must survive at least 3.0 grams of force. If not, the bonder parameters will be adjusted, and the qualification will return to step (1). 4) (Perform desired bonds on populated warm board.) 5) Perform 6 wire bonds from substrate to substrate on the fully-populated warm board. 6) Pull test wire bonds from step (5) to breaking (destructive testing). Record breaking force. If one or more is under 3.0 grams, the wire bond session will be 'flagged' for review. We will additionally: 7) Visually inspect all wire bonds on the fully-populated warm board for bond quality. Also verify that bond height is less than 0.090" from the top surface of the substrate. The approximate wire bonder settings, to be optimized and documented at the time of bonding the warm boards, are: 1) substrate temperature: 100 degrees C 2) force: 25 grams 3) ultrasonic power: 325 for dies, 375 for substrate 4) ultrasonic time: 30 msec Electrical Qualification ------------------------ Each JFET substrate holds 128 JFETs, divided into 4 groups of 32. The groups are labeled 'A' through 'D' on the warm board. A group of 32 devices services half each of two rows of detectors. For the cold test, the warm board will be brought to a temperature of 120 K +- 10 K. The JFETs will be operated with 5 V common drain, a voltage near 0 V on the gate, and a drain-to-source current of approximately 18 microA produced by connecting the source to a regulated -9 V supply through a 500 kohm resistor. 1. For 31 of 32 JFETs within each group, the following electrical characteristics will be met: a) Follower operation. The JFET source terminal responds to a small voltage increase at the gate with a gain of 0.99+-0.02. b) For 0 V gate voltage, the source voltage is between 0.200 V and 0.800 V. c) voltage noise <= 30 nV Hz^-1/2 at 3 Hz d) voltage noise <= 20 nV Hz^-1/2 at 10 Hz e) voltage noise <= 16 nV Hz^-1/2 at 30 Hz 2. For 28 of 32 JFETs, the following electrical characteristics will be met: a) voltage noise <= 15 nV Hz^-1/2 at 3 Hz b) voltage noise <= 10 nV Hz^-1/2 at 10 Hz c) voltage noise <= 8 nV Hz^-1/2 at 30 Hz 3. For all 6 heaters: a) Following the application of 7 mA through the heater for 10 minutes, the heater will be continuous and have resistance 2000+-100 ohms. 4. For both diodes: a) For a 10 microA excitation, the diode voltage will give a voltage 0.950+-0.050 V. Documentation ------------- 1. A record will be made for each epoxy batch and the hardness check. The epoxy mixing will be recorded quantitatively, while the hardness and adhesion check will be 'pass/fail'. 2. A record will be made of each wire bonding session, including the instrument settings and numerical pull test results. A 'pass/fail' record will be made for the visual inspection. 3. The JFET electrical qualifications for each device (items 1 and 2 above) will be recorded quantitatively. Qualification Plan Approval --------------------------- Arlin Bartels Darren Dowell (Caltech) Jeff Groseth (Caltech) Al Harper Murzy Jhabvala Dale Sandford George Voellmer